1. Field of the Invention
The invention relates generally to data processing systems and, more particularly, to modulation encoding subsystems.
2. Background Information
Data represented by multiple-bit symbols may be transmitted over a communications channel in the form of an analog signal, with ones represented by signal amplitudes above a predetermined first value and zeros represented by signal amplitudes below a predetermined second value. The bit transitions from ones to zeros and zeros to ones are thus represented by signal fluctuations. As appropriate, the communications channel may include magnetic media on which the data are recorded as a series of magnetic flux transitions, with a given direction representing a one and an opposite direction representing a zero. A bit transition is thus recorded as a change in flux direction, and the system recovers the recorded information by reading the flux transitions to recreate the analog signal. A decoding subsystem converts the recovered or received analog signal to a digital signal and recovers the digital information contained therein by first sampling the analog signal and, using an analog-to-digital (A/D) converter in a conventional manner, representing the signal samples as digital values. The system then detects the bits, that is, assigns bit values, i.e., ones and zeros, to the sampled signal based on the digital values. To provide accurate samples for bit detection, the system must sample the analog signal at times that correspond to the respective bits.
As is well known in the art, the A/D converter takes signal samples at times dictated by the pulses produced by a timing circuit. The timing circuit typically includes a phase locked-loop (PLL), which controls a clock that produces the sample timing pulses. If the PLL synchronizes the clock to the information contained in the analog signal, the clock pulses occur at one or more predetermined times during the signal segments that correspond to the respective bits.
The PLL controls the signal sample clock based on the timing of the bit transitions in the analog signal. In the absence of bit transitions, the PLL does not update the clock. Thus, sample timing errors, which adversely affect bit detection, may persist over segments of the data in which no transitions occur.
To minimize the sample timing errors, prior systems generally encode multi-bit symbols using a modulation code that limits the number of bits between signal transitions, that is, a code that limits the “run length” of consecutive 1's or 0's. The modulation code thus ensures that a signal transition corresponding to a transition from one to zero or zero to one occurs at least every “k+1” encoded bits. These codes, which are commonly referred to as k constraint codes, necessarily add bits to the data stream. A system designer selects a modulation code based on a desired run length and the associated bit overhead.
A modulation encoder using the k constraint code encodes the symbols in groups, to ensure that the run length constraints are met over the entire datastream. Otherwise, the run length may be violated by, for example, a symbol that includes multiple zeros as the least significant bits followed by a symbol that includes multiple zeros as the most significant bits. The modulation encoding schemes are thus relatively complex.
To reproduce the data, a demodulation decoder removes the k constraint code by similarly decoding the datastream as groups of symbols, after the analog signal has been converted to a digital signal and the bits detected. If a bit detection error occurs, such as assigning the wrong values to one or more bits in a group, the decoder may improperly decode multiple symbols of the group. The bit detection error thus propagates over the group.
Error correction codes (ECCs) are commonly used to encode the data symbols in such a manner that decoding errors can possibly be corrected. The ECCs are designed to correct a maximum number of symbols per data code word by including in the data code word a number of ECC symbols that are typically twice the number of correctable errors. When selecting an ECC code, the system designer must thus trade off the number of correctable errors versus ECC symbol overhead.
Increases in bit density tend to adversely affect bit detection in signals recovered from magnetic storage media. When bit transitions are recorded in adjacent cells and/or in smaller cells, the associated flux transitions tend to interfere with one another. The interference results in shifts in the size and locations of the bit transitions in the recovered analog signal, or what is commonly referred to as “intersymbol interference.” To minimize the adverse affects of such interference in the detecting of the bits, certain prior demodulation systems have used targeted-response finite impulse response filter (FIRS), also known as partial response or PRML, essentially to compensate for the effects of the interference. One such system is discussed in U.S. Pat. No. 6,249,398, which is assigned to a common assignee and incorporated herein by reference. The decoding system thus determines sample times and assigns bit values based on a filtered version of the received encoded analog signal.
The filtering works well as an aid to bit detection, however, the filtering does not necessarily aid the decoder in determining the times for sampling the analog signal.